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Enhanced Serial Audio Interface Timing
In I 2 C mode, the user may select a value for the programmed serial clock cycle from
to
6 × T C (if HDM[7:0] = $02 and HRS = 1)
4096 × T C (if HDM[7:0] = $FF and HRS = 0)
Eqn. 2
Eqn. 3
The programmed serial clock cycle (T I CCP ), SCL rise time (T R ), should be chosen in order to achieve the
2
desired SCL serial clock cycle (T SCL ), as shown in Table 22 .
44
SCL
46
50
49
51
48
53
45
52
SDA
Sto p Star t
47
MSB
58
LSB
55
ACK
56
Sto p
60
61
57
59
HREQ
Figure 13. I 2 C Timing
14
Enhanced Serial Audio Interface Timing
Table 22. Enhanced Serial Audio Interface Timing
No.
Characteristics 1, 2, 3
Symbol
Expression
Min
Max
Condition 4
Unit
62 Clock cycle 5
t SSICC
4 × Tc
22.3
—
x ck
ns
4 × Tc
22.3
—
i ck
63 Clock high period
? For internal clock
? For external clock
64 Clock low period
? For internal clock
? For external clock
t SSICCH
t SSICCL
2 × Tc
2 × Tc
2 × Tc
2 × Tc
12.0
12.0
12.0
12.0
—
—
—
—
ns
ns
65 SCKR edge to FSR out (bl) high
—
—
—
37.0
x ck
ns
—
22.0
i ck a
66 SCKR edge to FSR out (bl) low
—
—
—
37.0
x ck
ns
DSP56371 Data Sheet, Rev. 4.1
—
22.0
i ck a
48
Freescale Semiconductor
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